;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES OR INDEMNITIES.
;
;
; (C) Copyright 2006 Marvell International Ltd.
; All Rights Reserved
;

	OPT	2	; disable listing
	INCLUDE kxarm.h
    INCLUDE armmacros.s
	; debug
	INCLUDE monahans_base_regs.inc
    INCLUDE monahans_macros.inc

    OPT	1	; reenable listing
	OPT	128	; disable listing of macro expansions


	TEXTAREA
        
; *************************************************************************
	LEAF_ENTRY OEMARMCacheMode
;++
; Routine Description:
;    Sets the C and B bits to be used to build page tables
;
; C and B bits are part of the page table entries and control write through vs. write back cache
; modes, cacheability, and write buffer use. Note that C and B bit functionality is processor 
; specific and different for the 720, 920, and SA1100. Consult the CPU hardware manual for the CPU 
; in question before altering these bit configurations!!
; This default configuration (C=B=1)works on all current ARM CPU's and gives the following behaviour
; ARM720: write through, write buffer enabled
; ARM920: write back cache mode
; SA1100: write back, write buffer enabled
;
; The four valid options are:
;	ARM_NoBits		0x00000000   ; do not use
; 	ARM_CBit		0x00000008
; 	ARM_BBit		0x00000004   ; do not use
; 	ARM_CBBits		0x0000000C
;
; *Note:  XScale has altered the way the mini Dcache is configured.  It now uses
;         an additional bit, the 'X' bit, to designate a mini DCache configuration operation.
;
; Syntax:
;	DWORD OEMARMCacheMode(void);
;
; Arguments:
;	-- none --
;
; Return Value:
;	r0 must contain the desired C and B bit configuration. See description above for valid bit patterns.
;
; Caution: 
;	The value placed in r0 MUST be an immediate data value and NOT a predefined constant. This function
; 	is called at a point in the boot cycle where the memory containing predefined constants has NOT been 
;	initialized yet. 
;--

    ; *NOTE:  the kernel botches the address where this descriptor needs to live, so we cannot simply sneak a line into g_oalAddressTable
    ;   Need to write it ourselves before the kernel enables the MMU, and this is our only chance to do it.
    ; For NOR:  Write: 0x1000_040E to 5C00_0400, and 0x1010_040E to 5C00_0404 for 2MB mapping (for PT in IM).  
    ;
	
    ; **Need to change store address for DDR, IFF you change to a non-flat map.  Intenetions are that it will be.  The descriptor iteself is fine since it maps NOR**
    ; Again, for DDR, you do not need to do this if you map the virtual==phy==8000_0000.
    ;

    ;mrc     p15, 0, r0, c1, c0, 0               
    ;ands    r0, r0, #1                          
    ;bne     MMU_ON                              ; We have already enabled the MMU.  Bypass workaround.

    ;ldr     r0, =0x1000040E
    ;mov     r1, #0x5C000000
    ;orr     r1, r1, #0x00000400
    
    ;ldr     r0, =0x5C00040E             ; map IM=IM
    ;ldr     r1, =0x5C091700
    
    ;str     r0, [r1]                    ; map 1MB
    
    ;ldr     r0, =0x1010040E
    ;ldr     r1, =0x5C000404
    ;add	   r1, r1, #4
    ;str     r0,[r1]                     ; map 2MB.  Will make all of this dynamic ASAP.

    ;ldr     r4, =0x40100000                 
    ;mov   r12, #0x33
    ;strb   r12, [r4, #0]

    
    ; DMD workaround, part 1.  See dbgserial.c for part 2.
    ; Alter the descriptor the kernel just wrote that is error-prone
    ; Assume r4 contains the base adress of PT. Next step is to use kernel export symbol.
    
  IF :DEF: DMD_WORKAROUND
          
    mrc     p15, 0, r0, c1, c0, 0           ; user mode hazard
    ands    r0, r0, #1                      ; flags hazard
    bne     MMU_ON                          ; We have already enabled the MMU.  Bypass workaround.

    ldr     r0, [r4, #0x340]
    orr     r0, r0, #0x0FF0                 ; (r0) = PTE for 64K, kr/w kr/w r/o r/o page, uncached unbuffered
    str     r0, [r4, #0x340]                ; store the entry into 8 consecutive slots
    
    ldr     r0, [r4, #0x344]    
    orr     r0, r0, #0x0FF0                 ; (r0) = PTE for 64K, kr/w kr/w r/o r/o page, uncached unbuffered
    str     r0, [r4, #0x344]

    ldr     r0, [r4, #0x348]
    orr     r0, r0, #0x0FF0                 ; (r0) = PTE for 64K, kr/w kr/w r/o r/o page, uncached unbuffered
    str     r0, [r4, #0x348]

    ldr     r0, [r4, #0x34C]
    orr     r0, r0, #0x0FF0                 ; (r0) = PTE for 64K, kr/w kr/w r/o r/o page, uncached unbuffered
    str     r0, [r4, #0x34C]
 

MMU_ON
  
  ENDIF
  
    mov	r0, #0x0000000C	         ; C=1,B=1; write back, read allocate

    RETURN

    END

